Home

About Us

Product Center

Place & Route Platform STA/POWER

Join Us

Join Us Huaxin Life

Contact Us

Place & Route Platform
Delivering solutions from RTL to GDSII
Huaxin Place & Route Platform delivers comprehensive digital implementation solutions from RTL to GDSII, featuring:
•    Complete implementation flow: floorplanning, placement, clock tree synthesis (CTS), optimization, and routing 
•    Optimal PPA and TAT solutions driven by chip manufacturing and yield
•    Established nodes and advanced FinFET nodes support
•    Industry-standard input file compatibility 
•    User-friendly scripting and configurable design flow
With specific Litho Friendly Design technique that realizes bi-directional data communication between the backend design flow and the downstream OPC flow, the tool facilitates design closure,minimizes design iteration, and decreases time to market for your product
User-friendly GUI
for floorplan and powerplan
Support for timing-driven
and routability-driven placement
Minima-latency clock tree synthesis
with automated optimization
Support for advanced-node
double-patterning routing
Key Features and Benefits
Massively parallel computing and multi-threaded architecture for optimal PPA and faster TAT
Performance optimization under strict power/area constraints
Frequency target achievement with minimized power/area overhead
Tightly integrated with unified UI and common data model
Advanced-node support: 28nm/14nm/12nm and below
Leading-edge placement algorithms with advanced DRC checking/fixing capabilities
AMP-based macro placement for superior PPA targets
Solver-based placement engine with timing- and routing-driven optimization
CTS-aware placement for enhanced clock tree quality
Litho-Friendly routing and optimization engine with tight OPC tool integration
Advanced congestion-aware routing algorithms
Accurate DRC correlation with physical verification tools