On November 11, the 2023 China Integrated Circuit Design Annual Conference and Guangzhou Integrated Circuit Industry Innovation Development Summit (ICCAD 2023), themed "Bay Area Unites, Core Towards the Future," successfully concluded in Guangzhou. The event consisted of an opening ceremony, a summit forum, seven thematic seminars, and an industry exhibition. Over 4,000 industry professionals from around the world attended, making it the largest conference in its history with record-breaking participation. Huaxin Jushu was invited to participate in the event, engaging with industry partners to discuss innovation and development in the integrated circuit industry.
During the two-day exhibition, Huaxin Jushu showcased its HXOPT, a new-generation domestic digital full-flow design platform. The platform provides end-to-end solutions for digital backend design, from RTL to GDS, including floorplanning, placement, clock tree synthesis, and routing, as well as timing, physical, and power analysis. It offers optimization solutions for key metrics such as performance, power, and area (PPA), delivers improved turnaround time (TAT), and supports multiple mainstream and advanced process technologies. The platform accepts industry-standard file formats as input and provides user-friendly script configuration and design flow. Its unique Litho Friendly Design technology incorporates lithography considerations into the backend design process, ensuring robust product yield.
At the exhibition, Huaxin Jushu also launched a scan-and-win activity, attracting numerous attendees to stop by and engage in discussions. The Huaxin Jushu team warmly received visitors and provided professional technical explanations.
On November 10, Dr. Liu Tong from Huaxin Jushu delivered a keynote speech titled "New-Generation Digital Backend Design EDA Platform" at the "EDA and IC Design" sub-forum.
Addressing how to better support the domestic chip industry, Huaxin Jushu emphasized that while catching up technologically with the "Big Three" (leading EDA companies), it is essential to strengthen the connection between front-end and back-end design tools, as well as the link between design tools and manufacturing tools. By enabling collaborative optimization across the flow, design outcomes can be significantly improved. Therefore, while primarily developing backend design tools to achieve a full-flow chip design solution, Huaxin Jushu is committed to enhancing the collaborative optimization process between backend design tools, frontend design tools, and manufacturing tools, providing a yield-driven domestic full-flow solution for chip backend design and verification.
In addition to supporting backend design functionalities, Huaxin Jushu is also advancing collaborative optimization with frontend design tools and manufacturing tools, aiming to build an integrated chip design platform from RTL to wafer. By integrating with frontend design tools, HXOPT enables re-synthesis functionality. Leveraging frontend design capabilities for netlist restructuring and optimization, it optimizes critical timing paths during the backend design process, thereby enhancing overall design quality. Through integration with manufacturing-side computational lithography (OPC) tools, HXOPT implements lithography-optimized routing. Based on OPC tools' accurate predictions of process behavior, it identifies and repairs lithography hotspots during the backend design phase, delivering superior manufacturing outcomes and improving tape-out yield.
Dr. Liu pointed out that since the 14th Five-Year Plan explicitly identified EDA as a key software requiring breakthrough, achieving secure, independent, and controllable chip design tools has risen to a national strategy. While facing such industry challenges, the realization of domestic EDA tools can also change the landscape dominated by the "Big Three" in the domestic market, creating significant opportunities for localization. Under such challenges and opportunities, hundreds of EDA companies have emerged in China. Overcoming the technological barriers of the "Big Three" and meeting the domestic chip industry's demand for EDA tools are critical considerations for all EDA companies.
